Low-Power and Space-Efficient Built In Self-Test Architecture With MSIC Test Pattern Generator

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Kolanchinathan V P
Dinesh Kumar T R
Jaishree P
Niranjana M
Sowmiya M
Thresha V
Pooja sri K

Keywords

BuiltInSelfTest(BIST), Multiple single input change(MSIC), Test pattern generator(TPG), fault coverage, pseudorandom test pattern

Abstract

The new low-cost test pattern generation approach for a Multiple Single Input Change (MSIC) test pattern BIST architecture. BIST is a methodology that uses on-chip test logic to identify problematic system components. To increase fault coverage, the authors propose using a test pattern generator that creates MSIC test patterns and weights the pseudorandom test patterns. The goal is to provide an effective weighted TPG for a BIST architecture based on scans that requires less space and power usage. To maximize the length of the weighted pseudorandom patterns, the authors use a TPG pseudo-primary seed and a weight-enabled clock to provide distinct weights to the various scan chains. By this method, the hardware overhead is decreased and 0.215 μW power usage is achieved . The proposed weighted TPG produces accurate results when applied to two alternative test-per-scan BIST architectures, with fewer switching transitions, larger fault coverages, and less delay of 0.170 μs and area compared to existing methods. This behavior is observed for six additional circuits being tested. In order to compare the suggested balanced TPG with other potential designs, it is also scaled up to a larger bit TPG. The experimental findings are compared and contrasted with those of other TPG designs.

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